1. Field of the Invention
The invention relates generally to vertical semiconductor power devices. More particularly, this invention relates to configurations and methods implemented with a single thin epitaxial layer with improved manufacturability for manufacturing flexibly scalable charge balanced vertical semiconductor power devices with a super-junction structure and shielded gate trench with simple manufacturing processes flexibly adjustable for applications to different targeted breakdown voltages.
2. Description of the Prior Art
Conventional manufacturing technologies and device configuration to further increase the breakdown voltage with reduced series resistance are still confronted with manufacturability difficulties. The practical applications and usefulness of the high voltage semiconductor power devices are limited due to the facts that the conventional high power devices generally have structural features that require numerous time-consuming, complex, and expensive manufacturing processes. As will be further discussed below, some of the processes for manufacturing the high voltage power devices are complicated thus having low throughput and low yields. Furthermore, instead of using a raw semiconductor wafer, the semiconductor power devices are generally fabricated with preprocessed wafer formed with an epitaxial layer thereon. The production costs of the semiconductor power devices are therefore increased. Also, the functionality and performance characteristics are often dictated by the process parameters applied in forming this epitaxial layer. For these reasons, the application of such preprocessed wafers further limits the manufacturability and the production flexibility of the power devices that are now dependent on the original preprocessed wafer employed to manufacture the semiconductor power devices.
In comparison to conventional technologies, the super-junction technologies have advantages to achieve higher breakdown voltage (BV) without unduly increasing the drain-to-source on resistance, Rdson. For standard power transistor cells, breakdown voltage is supported largely on the low doped drift layer. Therefore, the drift layer is made with greater thickness and more resistive at higher voltage ratings. However this has the effect of greatly increasing the Rdson. In conventional power devices, the Rdson has approximately a functional relationship represented by:Rdson∝BV2.5In contrast, a device having a super-junction configuration is implemented with a charge balanced drift region. The resistance Rdson has a more favorable functional relationship with the breakdown voltage. The functional relationship can be represented as:Rdson∝BVFor high voltage applications, it is therefore desirable to improve the device performance by designing and manufacturing the semiconductor power devices with super-junction configurations for reducing the resistance Rdson while achieving high breakdown voltage. Regions adjacent to the channel within the drift region are formed with an opposite conductivity type. The drift region may be relatively highly doped, so long as the regions adjacent to the channel are similarly doped but of an opposite conductivity type. During the off-state, the charges of the two regions balance out such that the drift region becomes depleted, and can support a high voltage. This is referred to as the super-junction effect. During the on-state, the drift region has a lower resistance Rdson because of a higher doping concentration.
However, conventional super-junction technologies still have technical limitations and difficulties when implemented to manufacture the power devices. Specifically, multiple epitaxial layers and/or buried layers are required in some of the conventional structures. Multiple etch back and chemical mechanical polishing (CMP) processes are necessary in many of the device structures according to the previous manufacturing processes. Furthermore, the manufacturing processes often require equipment not compatible with standard foundry processes. For example, many standard high-volume semiconductor foundries have oxide CMP (chemical mechanical polishing) but do not have silicon CMP, which is required for some superjunction approaches. Additionally, these devices have structural features and manufacturing processes not conducive to scalability for low to high voltage applications. In other words, some approaches would become too costly and/or too lengthy to be applied to higher voltage ratings. As will be further reviewed and discussions below, these conventional devices with different structural features and manufactured by various processing methods, each has limitations and difficulties that hinder practical applications of these devices as now demanded in the marketplace.
A conventional type of semiconductor power device for high voltage applications includes those devices formed with standard structures as depicted in FIG. 1A for a standard VDMOS that do not incorporate the functional feature of charge balance. For this reason, there is no breakdown voltage enhancement beyond the one-dimensional theoretical figure of merit, i.e., the Johnson limit, according to the I-V (current-voltage) performance measurements and further confirmed by simulation analyses of this type of devices. The devices with this structure generally have relatively high on-resistance due to the low drain drift region doping concentration in order to satisfy the high breakdown voltage requirement. In order to reduce the on resistance Rdson, this type of device generally requires large die size. Despite the advantages that the devices can be manufactured with simple processes and low manufacturing cost, these devices are however not feasible for high current low resistance applications in the standard packages due the above discussed drawbacks: the die cost becomes prohibitive (because there are too few dies per wafer) and it becomes impossible to fit the larger die in the standard accepted packages.
A second type of devices includes structures provided with two-dimensional charge balance to achieve a breakdown voltage higher than the Johnson limit for a given resistance, or a lower specific resistance (Rdson*Area product) than the Johnson limit for a given breakdown voltage. This type of device structure is generally referred to as devices implemented with the super junction technology. In the super junction structure, a charge-balance along a direction parallel to the current flow in the drift drain region of a vertical device, based on PN junctions and field plate techniques implemented in oxide bypassed devices to enable a device to achieve a higher breakdown voltage.
FIG. 1B is a cross sectional view of a device with super junction to reduce the specific resistance (Rsp, resistance times active area) of the device by increasing the drain dopant concentration in the drift region while maintaining the specified breakdown voltage. The charge balance is achieved by providing P-type (for n-channel devices) vertical columns formed in the drain to result in lateral and complete depletion of the drain at high voltage to thus pinch off and shield the channel from the high voltage drain at the N+ substrate. Such technologies have been disclosed in Europe Patent 0053854 (1982), U.S. Pat. No. 4,754,310, specifically in FIG. 13 of that Patent, and U.S. Pat. No 5,216,275. In the previous disclosures, the vertical super junctions are formed as vertical columns of N and P type dopant. In vertical DMOS devices, the vertical charge balance is achieved by a structure with sidewall doping to form one of the doped columns as were illustrated in drawings. In addition to doped columns, doped floating islands have been implemented to increase the breakdown voltage or to reduce the resistance as disclosed by U.S. Pat. No. 4,134,123 and U.S. Pat. No. 6,037,632. Such device structure of super junction still relies on the depletion of the P-regions to shield the gate/channel from the drain. The floating island structure is limited by the technical difficulties due to charge storage and switching issues.
For super junction types of devices as described above, the method of manufacturing are generally very complex, expensive and require long processing time due to the facts that the methods require multiple steps and several of these steps are slow and have a low throughput. Specifically, the steps may involve multiple epitaxial layers and buried layers. Some of the structures require deep trenches through the entire drift region and require etch back or chemical mechanical polishing in most these processes. For these reasons, the conventional structures and manufacture methods are limited by slow and expensive manufacturing processes and are not economical for broad applications.
In U.S. application Ser. No. 12/005,878 filed by the inventor of this application, of which this application is a Continuation-In-Part, a super junction device with charge-balancing epitaxial columns grown in deep trenches is disclosed. Trench metal oxide semiconductor field effect transistors (MOSFET) are formed in the top epitaxial layer grown over the deep trenches and the areas surrounding the deep trenches. However the trench gate of this device may experience high electric fields and may be vulnerable to damage during voltage breakdowns.
Thus, in addition, to the demands to improve the configurations and the methods of manufacture for the super-junction devices, there is also a requirement to shield the sensitive gates during the breakdown for the active cells. FIGS. 1C-1 to 1C-3 show the devices disclosed in U.S. Pat. No. 6,635,906 with devices formed with P-floating islands 1 in the bulk layer of the epitaxial layer. These P-floating islands are however not self-aligned to the gate or to trenches and have less effectiveness during the voltage breakdown in protecting the sensitive trench gates. FIG. 1D shows a figure disclosed by Takaya et, al., in their paper “Floating Island and Thick Bottom Oxide Trench Gate MOSFET (FITMOS),” at the 17th International Symposium on Power Semiconductor Devices & IC's in 2005, showing the floating P-regions implanted for charge balancing the drain and the P-region at the bottom of the trench gates are applied to separate the gate from the P-region. However, these p-implant regions below the trench gates are in contact with the gate trenches with a thick bottom oxide and may reduce the amount of current that can pass through during on operation.
Therefore, a need still exists in the art of power semiconductor device design and manufacture to provide new device configurations and manufacturing method in forming the power devices such that the above discussed problems and limitations can be resolved.